RISC-V is an open-source instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles. It is considered the fifth generation of processors built on the concept of RISC. Unlike proprietary processor architectures, RISC-V is an open-source ISA used for the development of custom processors targeting a variety of end applications, from embedded designs to supercomputers. RISC-V is provided under royalty-free open-source licenses, and it is defined by member companies of RISC-V International, the global nonprofit organization behind the ISA. The RISC-V ISA provides the flexibility to pick and choose from available features, rather than having to use the full feature set.

Some key features of RISC-V include:

• Modular technical approach: RISC-V combines a modular technical approach with an open, royalty-free ISA, meaning that anyone, anywhere can benefit from the IP contributed and produced by RISC-V.
• Design freedom: RISC-V International is wholly committed to design freedom, choice, and flexibility, and supports open architecture extensions to the RISC-V ISA.
• Flexibility: RISC-V offers a unique set of features that allow users to customize and optimize both software and hardware for specific use cases.
• Load-store architecture: Like many RISC designs, RISC-V is a load-store architecture: instructions address only registers, with load and store instructions conveying data to and from memory.

RISC-V began as a project at UC Berkeley to create an open-source computer system based on RISC principles. The standard has since been developed and maintained by RISC-V International, a Swiss nonprofit business association. RISC-V has gained popularity in recent years due to its openness and technical merits. It has been incorporated into microcontrollers and embedded devices, and it is becoming mainstream in the marketplace.